1. Field of the Invention
The present invention relates to a semiconductor device having a high breakdown voltage structure.
2. Related Art
Generally, power ICs are classified by both of a low voltage and a high breakdown voltage device, and widely used, for example, in an automotive industry. Environment for an automotive semiconductor device is severe. Therefore, protection at relatively higher level is required with respect to Electrostatic discharge (ESD) or other kinds of electrical transient phenomena. ESD is considered as a high energy pulse produced when a person or an object bearing electric charges touches an IC.
As a method of protecting the semiconductor device from ESD, it is considered that a resistance element is inserted between a semiconductor device and an output pin to limit a current accompanied with Electrostatic discharge. However, for LDMOS, a high breakdown voltage device, a low on-resistance and a high breakdown voltage are required. Therefore, it is not good to insert a resistance element, because the on-resistance property of LDMOS seen from a pad will be suffered.
As for the conventional LDMOS, when Electrostatic discharge occurs, a strong electric field is applied to a drain edge, and avalanche breakdown occurs, resulting in production of electrons and holes. Hole current flows through a base of a parasitic bipolar transistor in LDMOS to activate a parasitic bipolar transistor. As for its collector current, there is a problem that a local current concentration occurs at the drain edge, and thermal runaway occurs in the region, thereby, enough ESD immunity cannot be obtained. In addition, even if the parasitic bipolar remained inactivated, a high avalanche current locally increases the intensity of the electric field at the drain edge, thereby a thermal runaway also occurs at the drain edge (see; Japanese Patent Laid-Open No. 2001-352070).